Oskar
Zielinski

SystemVerilog / FPGA — individual project

• Designed an 8-point FFT butterfly core from algorithmic specification through to RTL and FPGA demonstration.
• Performed manual scheduling and resource binding into a clocked controller/datapath architecture with FSM and registered datapath.
• Implemented signed fixed-point DSP arithmetic — 8-bit twiddle-factor encoding, 16-bit intermediate multiplication, truncation back to 8-bit signed outputs.
• Shared multiplier resources across sequential states to reduce hardware cost.

SystemVerilog / FPGA — group project

• Implemented control logic for a 16-character LCD interface, including initialisation, command/data transfer, and busy-flag handshaking for an ST7066U-style display.
• Formatted rainfall and wind-speed sensor data into LCD-ready character output.
• Wrote testbenches verifying character writes, address handling, and reset behaviour; traced an unexpected extra rain pulse to a button-synchronisation flip-flop issue.
• Validated the full subsystem on Intel FPGA hardware.

FPGA-based Gaussian smoothing

• Designed a small 8-bit application-specific processor for Gaussian smoothing of signed waveform samples.
• Defined a minimal instruction/control sequence to poll inputs, read five ROM samples, multiply-accumulate against fixed kernel coefficients, and drive LED output.
• Verified in SystemVerilog testbenches, XCelium/SimVision simulation, Quartus synthesis analysis, and on FPGA hardware.

Undergraduate final year project

• Designed and simulated a complete 8-bit Von-Neumann CPU in Logisim Evolution — ALU, registers, FSM control, and control ROM driving a fixed fetch-decode-execute cycle.
• Verified arithmetic, memory access, branching and conditional halting via single-step simulation and DIP-switch stimulus.
• Documented an expansion roadmap covering an assembler toolchain, interrupt/stack support, and UART I/O.

Cell library project

• Designed a full-adder and other minor cells in Magic using two metal layers, adhering to DRC and enforcing I/O and height constraints for library integration.
• Produced stick diagrams and transistor-level schematics from Boolean equations, iterating layout to reduce area and interconnect length.
• Ran parasitic extraction (ext2spice) and automated delay/capacitance sweeps across load and slew corners, generating databook tables per input–output pair.

Medical electronics group project

• Contributed to a two-sensor forearm EMG system linking muscle activity acquisition to robotic-hand actuation.
• Worked on EMG preprocessing and decision logic — filtering, RMS feature extraction, and threshold classification into gesture commands.
• Helped integrate processed EMG output with a robotic hand via Python–Arduino serial communication and servo control.

• Built an Arduino-based line follower using IR sensors with ultrasonic obstacle detection.
• Implemented control logic to smooth steering and handle sensor dead zones.
• Compared Bluetooth vs RF for a custom remote; selected RF for range, latency, and ease of use.